1. Field of the Invention
The present invention relates to a high-precision sample-and-hold circuit device for driving a liquid crystal display or the like.
2. Description of the Related Art
According to a conventional sample-and-hold circuit device, a p-channel MOS transistor and an n-channel MOS transistor are connected in parallel with each other to constitute a MOS analog switch with one connection node being connected to an input terminal, and the other connection node being connected to a capacitor and an output terminal.
In the conventional sample-and-hold circuit device, control signals .phi.1 and .phi.2 having opposite phases are supplied to the gates of the parallel-connected MOS transistors to control an opening/closing operation of the MOS analog switch. When the MOS analog switch is set in a closed state by the control signals .phi.1 and .phi.2, charges are accumulated in the capacitor until the terminal potential of the capacitor reaches an input terminal potential. When the MOS analog switch is opened by the control signals .phi.1 and .phi.2, the charges accumulated in the capacitor are held. Such an operation is called a sample-and hold operation.
In the above sample-and-hold operation, if the sampling rate is increased, it is difficult that the conventional sample-and-hold circuit performs an ideal sample-and-hold operation. The reasons for this will be described below.
Stray capacitance called overlap capacitances are present between the gate electrode and the drain electrode and between the gate electrode and the source electrode of the MOS transistors. When the MOS switch is changed from a closed state to an open state by the control signals .phi.1 and .phi.2, the control signals leak from the gate electrodes into the capacitor through the overlap capacitor. The leaking signals serve as error charges and are superposed on the charges held in the capacitor. In addition, according to an operation principle of a MOS transistor, channel charges are generated in the channels of the two MOS transistors during an 0N state. When each MOS transistor goes to an OFF state at a very low speed, the channel charge flows in the one of the source and drain electrodes which has a lower impedance. In contrast to this, if each MOS transistor goes to an OFF state at a high speed, the channel charge branches and flows in both the source and drain electrodes. Therefore, if sampling rate is increased, a given percent of channel charges are superposed, as error charges, on the charges held in the capacitor.
A sample-and-hold circuit is applied to a driving circuit used for a liquid crystal display or the like. In this case, the above-described sample-and-hold circuit is connected to an input terminal, and an output buffer having an output enable terminal is connected to the sample-and-hold circuit. The output terminal of the output buffer is connected to a liquid crystal cell through a switch using a TFT (Thin Film Transistor). Note that a wiring capacitance on the liquid crystal display is formed between the nodes of the output buffer and the TFT.
According to the above-mentioned liquid crystal display driving circuit, the sample-and-hold circuit samples/holds a video signal by using the control signals .phi.1 and .phi.2 in a horizontal period of the video signal in which an effective video signal is sent (to be referred to as an effective period hereinafter). At this time, the output buffer is set in an OFF state by a control signal OE, and its output terminal is set in an high-impedance state. In a horizontal blanking period after a sample and-hold operation is performed, the wiring capacitance is charged to a sampled/held potential by a control signal OE. In addition, the liquid crystal cell is driven through the TFT which is set in ON state by a control signal Yc. Since the characteristics of the TFT are inferior to those of a normal MOS transistor, the TFT must be further kept in the ON state for a given interval A after the horizontal blanking period by using the control signal. When the output terminal of the buffer is set in an high-impedance state by the control signal OE, and the TFT is set in an ON state, the potential held in the wiring capacitance drives the liquid crystal cell through the TFT even in the interval A.
The conventional liquid crystal display driving circuit has the following drawback as well as errors and difference in characteristics among the sample-and-hold circuits. Since the wiring capacitance is energized by nothing in the liquid crystal display driving interval A, the driving circuit is susceptible to the influences of external noise, and deterioration in picture quality tends to occur. In order to eliminate such a drawback, a conventional sample-and-hold circuit may have a multistage arrangement. In a multistage sample-and-hold circuit, however, errors and differences in characteristics among the respective stages may be superposed on each other.
Furthermore, since all the sample and hold circuits corresponding to the number of pixels of one horizontal scanning line cannot be integrated into one IC, a large number of ICs incorporating a large number of sample-and-hold circuits are used to drive the display. In this case, considerable differences in brightness or color tone occur in the form of a strip at portions on the screen at which the respective ICs are driven, thus deteriorating the picture quality.
As described above, in the conventional technique, the first problem to be solved is associated with an error caused by leakage of control signals, supplied to the sample-and-hold circuit, to the output terminal, and an error caused by channel charges generated when the analog switch constituted by the MOS transistors is in an OFF state. Furthermore, in the IC incorporating a large number of sample-and-hold circuits applied to a driving circuit for driving a liquid crystal display or the like, difference in errors among the sample-and-hold circuits makes the picture quality further deteriorate. The second problem to be solved is associated with the drawback that with a sample-and-hold circuit having a single-stage arrangement, a TFT or a liquid crystal cell of a liquid crystal display can be driven in only a horizontal blanking period of one horizontal period, and hence external noise appears on the screen to deteriorate the picture quality. If a sample-and-hold circuit having a two-stage arrangement is used to prevent such a problem, output attenuation or variation is undesirably increased. In addition to the problems in ICs, the third problem to be solved must be considered, which is associated with the drawback that differences in brightness or color tone occur in the form of a strip at portions on the screen driven by the respective ICs, due to difference in characteristics among the ICs, so as to considerably deteriorate the picture quality.